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USB/I2S audio device interface using JP1/JP2

PostPosted: Wed May 13, 2015 4:30 pm
by edsut
I've seen some posts on this already, but nothing conclusive.
This is a 2-part question:
First the hardware...
I am working on an iMX6 based multimedia device that will be using a different
audio codec. The codec uses I2S for the data and I2C for control. I see from the
wandboard schematic that two sets of I2S lines (AUD3 & AUD5) are tied to the SGTL5000.
Looking at headers JP1 and JP2, it seems to me that I could reconfigure the following
pins (ALT4):


along with one of the I2C sets on JP2, to the wire up to an external codec.
Anyone see any reason why this can't be done?

Now the software:
Has anyone already configured the Wandboard through the USB-OTG port as
an usb audio device gadget? I'm new to USB development, so I may have phrased
that incorrectly.


Re: USB/I2S audio device interface using JP1/JP2

PostPosted: Fri May 15, 2015 6:14 am
by Tapani
We have not tried this.

The first catch I came and think about is the Audio clock, normally on pin 195 on the EDM connector. But it seems like you are lucky.
The CCM_CLK0 function can also be muxed onto GPIO_19 pin, which is one of the external GPIOs (pin 263 on the EDM connector).

So I cannot immediately say this will not work. Keep us posted!

Re: USB/I2S audio device interface using JP1/JP2

PostPosted: Tue May 19, 2015 5:52 pm
by edsut
Ok, thanks for looking into this.
This raises my level of confidence that it will work.
I will be starting on this almost immediately, and will post my results.

Re: USB/I2S audio device interface using JP1/JP2

PostPosted: Thu Jun 30, 2016 11:13 pm
by nad
Dear all,
I also wish to try to implement the wandboard with 3 audios (AUD3, AUD4, AUD5) that expands from the original Wandboard with one additional codec with pin connections like edsut found. For the software part, I have found it tough to do the resource allocation (SSI, DMA) and the ALSA/ASoc registration - how the system recognizse these three codecs. These tasks should be done with device tree and kernel driver modifications.
I am wondering if you have made any progress on this implementation, and if possible, can you please share some experiences here. I would be grateful for this